1. Field of the Invention
The present invention relates generally to semiconductor devices such as dynamic random access memories (DRAMs) having a capacitor and methods of manufacturing the same and particularly to those having a rough surface to increase the capacitance of a capacitor and also enhancing a margin preventing the short-circuit between capacitors.
2. Description of the Background Art
FIGS. 26-34 show a method of forming in a conventional DRAM an upper portion of a storage node of a stacked, cylindrical capacitor that has a rough surface. Note that an underlying region including a semiconducting active region, an underlying wiring and the like is not shown. In the conventional method of forming an upper portion of a storage node, initially, as shown in FIG. 26, a resist mask 103 is placed on an interlayer insulating film 101 formed of tetra-ethyl-ortho-silicate (TEOS) and a storage node contact hole 102 is thus opened in the interlayer insulating film. Then, resist 103 is ashed and thus removed. Then, as shown in FIG. 27, phosphorus doped amorphous silicon 104 is deposited to fill storage node contact hole 102. An underlying wiring and a storage node capacitor are connected by a plug interconnection of phosphorus doped amorphous silicon because phosphorus as a dopant can facilitate reduction in resistance and can readily be controlled. The amount of phosphorus doped is approximately 4 to 8xc3x971020/cm3. The film has a thickness of approximately 0.1 to 0.2 xcexcm, although it depends on the diameter of the storage node contact hole. Then, as shown in FIG. 28, the entire surface is anisotropically etched to remove the phosphorus doped amorphous silicon on the interlayer insulating film to leave the phosphorus doped amorphous silicon only in storage node contact hole 102. Then, a plug interconnection 104a is formed. Then, as shown in FIG. 29, a phosphorus doped, polycrystalline silicon film 105 is deposited and boro-phospho-tetra-ethyl-ortho-silicate (BPTEOS) 106 is then deposited. Phosphorus doped, polycrystalline silicon film 105 has a thickness of approximately 0.05 to 0.1 xcexcm. Then, as shown in FIG. 30, a resist mask (not shown) is used to etch BPTEOS 106 to form a pattern 106a of a storage node 107. Then, a combination of the resist mask and BPTOES 106a etched as above is used as a mask to etch a phosphorus doped, polycrystalline silicon film 105 to form a lower portion 105a of the storage node. At this stage, storage nodes 107 partially formed are spaced by a spacing 110. The geometry between storage nodes 107 is similar to various holes etched, providing an opening wider as it approaches the top, i.e., tapering toward the bottom. Then, as shown in FIG. 31, a non-doped amorphous silicon film 108 is deposited to later configure an upper portion of the storage node. Storage nodes 107 once separated at the FIG. 30 step are connected together at the FIG. 31 step. Non-doped amorphous silicon film 108 has a thickness of approximately 0.05 xcexcm. Then, to separate storage nodes 107 from each other, non-doped amorphous silicon film 108 has an entire surface anisotropically etched. Thus, the non-doped amorphous silicon film covering a top surface of geometry 106a of the storage node is also etched away and BPTEOS 106a is exposed (FIG. 32). Furthermore, the non-doped amorphous silicon film covering interlayer insulating film 101 between the storage nodes is also etched away, TEOS 101 of the interlayer insulating film is exposed, and storage nodes 107 are separated from each other by a spacing 110a (FIG. 32). Then, vapor-phase HF is employed to selectively etch BPTEOS 106a filling the cylindrical, non-doped amorphous silicon. Thus a framework 108a of an upper, cylindrical portion of the storage node is formed.
As micro-fabrication technology further advances, cylindrical surface areas cannot provide a capacitor with a sufficient capacitance and accordingly there is a demand for further increased surface areas. To satisfy the demand, the cylindrical surface as described above is roughened to provide an increased capacitance to accommodate microfabrication. A conventional process for providing a rough surface employs a method of selectively roughening a cylindrical surface. In this method, Si2H6 is initially introduced into a vacuum of approximately 700xc2x0 C. and 10xe2x88x926 to 10xe2x88x928 Torr and an intermediate product obtained at the FIG. 33 stage is placed in the flow of Si2H6 for a predetermined period of time to allow a silicon seed to adhere to the cylinder of a storage node. Si2H6 can be introduced for a period of time adjusted to prevent the silicon seed from adhering to TEOS 101 of the underlying interlayer insulating film. This process exploits the fact that depending on what the silicon seed adheres to the silicon seed has different incubation periods of time and has a shorter incubation period when it adheres to silicon than to oxide film. Then the product is annealed at approximately 700xc2x0 C. and the silicon seed adhering to the cylindrical, non-doped amorphous silicon receives silicon atom from non-doped amorphous silicon 8 and is thus grown to stick out from the surface. Since a protrusion is grown on the surface from the silicon seed adhering to the surface, recesses and protrusions result, as seen across the entire surface, to roughen the surface (FIG. 34). The silicon seed hardly adheres to any locations other than cylindrical, non-doped amorphous silicon 108a and the roughening is thus limited. Consequently, only cylindrical, non-doped amorphous silicon 108a has a surface selectively roughened to form upper portion 108b of the storage node having a rough surface.
If the storage node has upper portion 108b remaining as non-doped amorphous silicon, the capacitor depletes. To prevent this, the surface roughening process described above is followed by introducing PH3 to dope the non-doped amorphous silicon with phosphorus; if phosphorus-doped amorphous silicon, rather than non-doped amorphous silicon, is initially used, the phosphorus contained therein would prevent silicon atom from moving, as desired, to provide a rough surface. On upper portion 108b of the storage node that has a rough surface are deposited a capacitance insulating film and a top electrode for a capacitor (a cell plate) to complete the capacitor. The above described capacitor, with a surface roughened, can have a substantially increased area to satisfy a need for increased capacitance associated with microfabrication.
However, as shown in FIG. 34, a silicon seed is also grown from non-doped amorphous silicon adhering to a side surface of a lower portion 105a of the storage node. Thus, storage node 107 has a short-circuit margin corresponding to a spacing 110b and thus hardly ensured, which facilitates short-circuit between storage nodes. This tendency is more significant as microfabrication further advances, and a reconciliation of providing a rough surface to provide an increased capacitance and ensuring a short-circuit margin between storage nodes is now an issue to be addressed.
The present invention contemplates a semiconductor device having a rough surface to increase a capacitor in capacitance and simultaneously enhancing a margin preventing short-circuit between capacitors, and a method of manufacturing the same.
In accordance with the present invention the semiconductor device includes: a plug interconnection penetrating an insulating film and connected to an underlying wiring; and a storage node having a lower portion overlying the insulating film and free of a rough surface, and connected to the plug interconnection, and an upper portion overlying the lower portion without covering a side surface of the lower portion, and having the rough surface.
Typically, storage nodes are spaced by an etched trench. As such, the storage node tends to be narrower at a lower portion, which is closer to the insulating film, and the storage node tends to be wider at an upper portion, which is further away from the underlying wiring. For a conventional capacitor a storage node has a lower portion with a side surface also roughened and an insufficient short-circuit margin is thus provided between storage nodes. In contrast, in the present invention a storage node can have a lower portion free of such a rough surface and thus allowing storage nodes to be spaced farther apart or have a short-circuit margin larger than conventional. Thus in a microfabricated semiconductor device a capacitor can be increased in capacitance and in addition storage nodes can be provided with a short-circuit margin larger than conventional. Note that the capacitor is formed of a dielectric film deposited on the upper portion of the storage node, and a film of a cell plate (a top electrode of the storage node) deposited thereon.
The storage node can have an upper portion provided with a rough surface and an underlying, lower portion free of such a rough surface, whether the upper portion is formed in a cylinder or a rod. If it is formed in the cylinder its internal and external surfaces are roughened and if it is formed in the rod then its surface would be roughened. As such, whether a capacitor is a stacked-type, cylindrical, rough-surface capacitor or a thick film-stacked capacitor, the capacitor can be provided with an increased capacitance and between capacitors a large-circuit margin can be obtained.
In the present semiconductor device the storage node can have the lower portion formed of polycrystalline silicon doped with an impurity.
The impurity-doped polycrystalline silicon has a surface hardly roughened as a silicon seed adhering thereto hardly receives silicon therefrom. Thus the storage node has a surface rougher at an upper portion than at a lower portion. As has been discussed above, adjacent storage nodes have their respective upper portions spaced farther apart than their respective lower portions. As such, short-circuit can be avoided more reliably by preventing the storage node from having a lower portion with a rough surface and thus a small short-circuit margin. As has been discussed above, adjacent storage nodes have their respective upper portions spaced farther apart and if an upper portion of the storage node has a surface rougher than a lower portion of the storage node the short-circuit margin is hardly affected.
In the present semiconductor device the storage node can have the lower portion formed of metal film.
With the storage node having a lower portion formed of metal film, if in roughening a surface the lower portion has a silicon seed adhering thereto the lower portion, free of silicon required for growth, could not provide a growth protruding laterally or toward a storage node adjacent thereto. Adjacent capacitors can thus be provided with a short-circuit margin further ensured than when a storage node has a lower portion formed of doped polycrystalline silicon. Furthermore, metal film is smaller in resistance and a low-resistance contact with an underlying wiring can be provided.
In the present semiconductor device the plug interconnection and the lower portion of the storage node can be formed of a single metal film.
Thus the plug interconnection and the lower portion of the storage node do not have an interface therebetween and they are also formed of metal film, which is lower in resistance than doped polycrystalline silicon. Thus a low-resistance contact with an underlying wiring can be provided. Furthermore, the plug interconnection and the lower portion of the storage node can be provided in a single film deposition apparatus at a time to reduce the number of process steps. More specifically, the steps of etching the plug interconnection back, chemical, mechanical polishing, and the like can be eliminated.
In the present semiconductor device the metal film composing the lower portion of the storage node or the plug interconnection can be of Ti/TiN/Ti.
The metal film of Ti/TiN/Ti allows the plug interconnection and the lower portion of the storage node to be readily provided by using existing equipment, have low resistance and have high stability both in fabrication and use.
In the present semiconductor device the plug interconnection and the lower portion of the storage node can be formed of polycrystalline silicon doped with an impurity.
Thus the plug interconnection and the lower portion of the storage node can have reaction stability superior to those of metal film in fabrication and use. Furthermore, the plug interconnection and the lower portion of the storage node can be provided in a single film deposition apparatus at a time to eliminate the steps for example of etching the plug interconnection back, chemically, mechanically polishing, and the like.
The present invention provides a method of manufacturing a semiconductor device including the steps of: providing a plug interconnection penetrating an insulating film formed to cover an underlying region including a semiconducting active region and an underlying wiring, to connect with the underlying wiring; providing on the insulating film a lower layer of a storage node connected to the plug interconnection; on the lower layer intact or on the lower layer with a predetermined pattern formed of an insulating film and arranged thereon, depositing an amorphous silicon film to be used to form an upper portion of the storage node; patterning both the amorphous silicon film and the lower layer and thereby forming on the insulating film the storage node having a lower portion and the upper portion; and roughening a surface of the amorphous silicon film forming the upper portion.
This ensures that the semiconductor device is provided with an increased capacitance of a capacitor and an increased short-circuit margin between adjacent capacitors. Furthermore, on the upper portion of the storage node that has a rough surface, as described above, a dielectric film can be deposited and thereon a film of a cell plate can be deposited to provide a capacitor.
In the present method, the step of depositing an amorphous silicon film includes forming a pattern of a rod on the lower layer and depositing the amorphous silicon film on the lower layer and the pattern, and the step of patterning and thereby forming includes removing the pattern and forming the upper portion in a form of a cylinder.
Thus a semiconductor device can be fabricated including a stacked-type, cylindrical, rough-surface capacitor increased in capacitance and short-circuit margin.
In the present method, the step of patterning and thereby forming includes the step of anisotropically etching away the amorphous silicon film covering an upper surface of the pattern of the rod, the amorphous silicon film covering the lower layer, and the lower layer covered with the amorphous silicon film, while leaving the amorphous silicon film covering a side surface of the pattern of the rod, and the step of removing the pattern of the rod having the upper surface exposed in the step of anisotropically etching, to form the upper portion formed of the amorphous silicon film provided in the form of the cylinder.
Thus, existing equipment can be used to precisely control the anisotropic etching step to prevent the storage node from having a lower portion with a rough surface, while allowing the storage node to have an upper portion provided with a rough surface. This ensures that a stacked-type, cylindrical, rough-surface capacitor has an increased capacitance and that adjacent capacitors also have an increased short-circuit margin therebetween.
In the present method, the step of forming a pattern of a rod includes providing a moisture-containing insulating film and patterning the moisture-containing insulating film in the rod, and the step of removing the pattern of the rod includes removing the moisture-containing insulating film through vapor-phase HF.
Vapor-phase HF only reacts with moisture-containing layers. Since phosphorus-containing BPTEOS contains moisture, vapor-phase HF can be employed to anisotropically etch only BPTEOS of a geometry corresponding to the upper portion of the storage node. Thus a significantly simple process can be used to form a cylindrical capacitor having internal and external surfaces contributing to providing an increased capacitance.
In the present method, the insulating film penetrated by the plug interconnection is a moisture-free, tetra-ethyl-ortho-silicate (TEOS) film and the insulating film forming the pattern of the rod is a moisture-containing, boro-phospho-tetra-ethyl-ortho-silicate (BPTEOS) film, and the step of removing the pattern of the rod includes removing the BPTEOS film through vapor-phase HF.
Vapor-phase HF can react only with moisture-containing layers and thus etch them. In BPTEOS a phase containing phosphorus contains moisture, whereas TEOS does not contain moisture. As such, vapor-phase HF reacts only with BPTEOS and etches the same. It does not react with the insulating film of TEOS exposed underlying the lower portion of the storage node and it reacts only with BPTEOS surrounded by cylindrical amorphous silicon and thus removes the same. Thus a stacked-type, cylindrical, rough-surface capacitor can readily be fabricated.
In the present method, the step of depositing the amorphous silicon film includes depositing the amorphous silicon film directly on the lower layer, the step of patterning and thereby forming includes etching away both the amorphous silicon film and the lower layer to form on the insulating film the storage node having the upper portion and the lower portion in the form of the rod.
Thus, existing equipment can be used to readily fabricate a semiconductor device including a thick film-stacked capacitor increased in capacitance and short-circuit margin.
In the present method a non-doped amorphous silicon film can be deposited in the step of depositing the amorphous silicon film.
Amorphous silicon is more effective than polycrystalline silicon in supplying a silicon seed adhering to a surface with silicon atoms to facilitate growth and thus roughen the surface. It is, however, less effective when it contains an impurity such as phosphorus. The non-doped amorphous silicon film used as the amorphous silicon film allows the storage node to have an upper portion provided with a surface significantly roughened to be more distinctively distinguished in roughness from a surface of the lower portion of the storage node free of such a rough surface. Thus if the lower portion of the storage node is formed of doped polycrystalline silicon it can be free of a rough surface while the upper portion of the storage node can be provided with a sufficiently rough surface to provide a large difference in roughness between the surfaces of the upper and lower portions of the storage node.
In the present method, the step of providing the plug interconnection includes depositing an impurity-doped polycrystalline silicon in a previously opened contact hole of the storage node, and the step of providing the lower layer includes subsequently, successively depositing the impurity-containing polycrystalline silicon, to provide the plug interconnection and the lower layer.
Thus the plug interconnection and the lower portion of the storage node can be free of any interface therebetween and a low-resistance contact with an underlying wiring can be provided. Furthermore, in providing the plug interconnection it is not necessary to provide for example the step of providing a deposition to fill a contact hole and then anisotropically etching an entire surface. This can reduce the number of process steps including the steps of etching the plug interconnection back, chemically mechanically polishing, and the like.
In the present method, the step of providing the plug interconnection includes depositing a metal film in a previously opened contact hole of the storage node, and the step of providing the lower layer includes subsequently, successively depositing the metal film, to provide the plug interconnection and the lower layer.
Thus the plug interconnection and the lower portion of the storage node can be free of any interface therebetween and metal film, smaller in resistance than doped polycrystalline silicon, can be used to provide a low-resistance contact with an underlying wiring. Furthermore, in providing the plug interconnection it is not necessary to provide for example the step of providing a deposition to fill a contact hole and then anisotropically etching an entire surface. Thus the number of process steps can be reduced.
In the present method the metal film deposited in at least one of the step of providing the plug interconnection and the step of providing the lower layer, is of Ti/TiN/Ti.
The metal film of Ti/TiN/Ti allows the plug interconnection and the lower portion of the storage node to be readily provided by using existing equipment, have low resistance and have high stability both in fabrication and use.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.